The present invention relates generally to integrated circuits (ICs) and more particularly to a phase selection circuit that avoids glitches in the output signal during phase switching.
Phase selection is a popular technique used in digital timing recovery and digital phase locked loops (PLLs). Digital timing recovery and digital PLL schemes are well known in the art. In one circuit application, a clock generation source generates multi-phase clock signals with different phases. The circuit may include a multiplexer (MUX) that selects one clock signal with a given phase to be supplied as a single output clock. As applied to a PLL for example, a selected phase or clock can then be fed to a PLL for comparison.
A problem with the method described, however, is the potential for glitches in the output signal when the MUX is switching from one phase to another. Signal glitches are difficult to avoid, especially at high speeds. FIG. 1 shows a timing diagram illustrating the operation of a conventional phase selector that produces a glitch (undesirable clock transition edges) when the output switches from one clock (phase) signal to another.
Still referring to FIG. 1, two phases or clock signals Phase 2 and Phase 3 from a clock-generating source are muxed to an output Outclk of a phase selector. While other clock signals (not shown) could also be present, the example shows two for ease of illustration. A mux selection signal (not shown) switches the output Outclk from one phase to another. As shown, if the mux selection signal switches from Phase 2 to Phase 3 at time t1, during the instant when Phase 2 is low and before Phase 3 goes low, a glitch would arise at output Outclk. Similarly, if the mux selection signal switches the output from Phase 2 to Phase 3 after Phase 2 goes high and before Phase 3 goes high, a glitch would arise. The duration of the glitch would depend on the precise time the transition occurs.
Such glitches at the phase selector output are undesirable because they cause erroneous output. Problems can manifest, for instance, when such a glitch triggers a counter. At high speeds timing the phase transition to avoid such glitches becomes increasingly difficult and unpredictable due to inherent delays in switching logic gates. Such propagation delays may prevent proper synchronization of the MUX transition to avoid the glitch.
With the ever-increasing demand for higher speed of operation for integrated circuits, there is a need for a phase selection circuit that avoids glitches in the output signal during phase switching.
The present invention satisfies these needs with a phase selection circuit that can operate without glitches at the output at both low and high speeds of operation while sustaining device functionality.